在設(shè)計(jì)中,所有的算數(shù)運(yùn)算符都是按照無符號(hào)數(shù)進(jìn)行的。如果要完成有符號(hào)數(shù)計(jì)算,對(duì)于加、減操作通過補(bǔ)碼處理即可用無符號(hào)加法完成。對(duì)于乘法操作,無符號(hào)數(shù)直接采用“*”運(yùn)算符,有符號(hào)數(shù)運(yùn)算可通過定義輸出為 signed 來處理。
通過“*”運(yùn)算符完成有符號(hào)數(shù)的乘法運(yùn)算。
module ceshi (out, clk, a, b);
output [15:0] out;
input clk;
//通過 signed 關(guān)鍵字定義輸入端口的數(shù)據(jù)類型為有符號(hào)數(shù)
input signed [7:0] a;
input signed [7:0] b;
//通過 signed 關(guān)鍵字定義寄存器的數(shù)據(jù)類型為有符號(hào)數(shù)
reg signed [7:0] a_reg;
reg signed [7:0] b_reg;
reg signed [15:0] out;
wire signed [15:0] mult_out;
//調(diào)用*運(yùn)算符完成有符號(hào)數(shù)乘法
assign mult_out = a_reg * b_reg;
always@(posedge clk)
begin
a_reg <= a;
b_reg <= b;
out <= mult_out;
end
endmodule
上述程序在 ISE 中的綜合結(jié)果如下圖所示,從其 RTL 結(jié)構(gòu)圖可以看到乘法器標(biāo)注為“signed” ,為有符號(hào)數(shù)乘法器。
仿真結(jié)果圖
二進(jìn)制顯示的結(jié)果